The present invention relates to interconnects for printed circuit boards, particularly those that contain memory devices.
Certain computer systems may employ a serial bus to transmit signals between a memory controller and memory. An example of such a serial bus has been defined by Rambus Corporation of Mountain View, California. That bus, often called the Direct Rambus memory channel, enables transmission of high speed, pipelined signals between a memory controller and memory. A memory card or module coupled to the bus may contain a number of high speed DRAMs, which have a Rambus developed architecture. Such memory devices are often called xe2x80x9cRambus DRAMsxe2x80x9d or xe2x80x9cRDRAMs.xe2x80x9d
The Direct Rambus memory channel requires signals to travel through all memory devices until terminated. Those memory devices add capacitance to the signal line, which lowers line impedance at those devices, when compared to the impedance of unloaded portions of the channel. That impedance discontinuity could adversely affect system performance, e.g., by requiring reduction in the maximum frequency at which high speed, pipelined electrical signals may be driven along the interconnectxe2x80x94to prevent signal reflection that may degrade signal quality.
To mitigate this effect, a design has been proposed in which the impedance of another portion of the signal line is raised to compensate for the reduced impedance at the memory devices. As shown in FIG. 1, which represents a printed circuit board (xe2x80x9cPCBxe2x80x9d) that contains several memory devices, relatively short high impedance lines 1 may be placed between memory devices 2 and unloaded portions 3 and 4 of the signal trace. (Dashed box 5 serves to indicate that PCB 10 may include memory devices in addition to those shown, which may be mounted to both sides of PCB 10. PCB 10 may, for example, include 16 memory devicesxe2x80x948 on each side.) By adjusting the length of lines 1, the average impedance resulting from the combination of lines 1 and memory devices 2 can closely match the impedance of the unloaded portions of the channel (e.g., unloaded portions 3 and 4 on PCB 10 and unloaded portions that are located on a motherboard designed to receive PCB 10). When the average impedance that results from combining lines 1 and memory devices 2 is approximately equal to that of the unloaded portions of the channel, the portion of the signal trace that lies between points 6 and 7 may, for all practical purposes, be treated as an extension of unloaded portions 3 and 4.
To achieve an impedance match between the loaded and unloaded portions of a signal line, a certain amount of PCB surface area is required to accommodate the high impedance traces. To reduce the size of the PCB, it may be necessary to reduce the amount of PCB xe2x80x9creal estatexe2x80x9d that is allotted to those traces. Accordingly, there is a need for an improved PCB interconnect that enables an impedance match between the loaded and unloaded portions of the signal line while allocating less PCB surface area to the high impedance traces. The present invention provides such an interconnect.